AMD and Qblox Collaborate on Quantum-Classical Feedback Loop

AMD and Qblox have announced a collaboration to address one of the critical challenges in fault-tolerant quantum computing: the development of a real-time quantum-classical feedback loop for error correction. This partnership combines Qblox's control stack technology with AMD's high-performance computing hardware to enable efficient quantum error correction (QEC) within the coherence window of qubits.

Building the Quantum-Classical Feedback Loop

Fault-tolerant quantum computing requires a seamless feedback loop where measurement data from qubits is processed by classical computing systems, decoded, and returned as corrections in real time. Qblox contributes its modular Cluster system, which includes synchronized control and readout modules connected via the LINQ feedback network and synchronized by SYNQ. AMD complements this with its Adaptive SoCs, FPGAs, Instinct™ GPUs, and EPYC™ server CPUs, forming the classical compute backbone.

The feedback loop crosses two critical boundaries. The first is within the control stack, where FPGA-based modules coordinate circuit executions and read out qubits. The second is between the control stack and the classical compute fabric, where quantum error correction algorithms are executed. This collaboration focuses on optimizing the second boundary by creating a direct, low-latency interconnect between the control system and accelerator memory.

Technical Innovations in the Interconnect

The interconnect developed by AMD and Qblox uses an Aurora link to transfer data between the control system and an AMD Alveo™ U55C link card. This link operates over four lanes at 10.3125 Gb/s each, using AMD's lightweight point-to-point serial protocol. The Aurora plug-in delivers frames as 512-bit words at 250 MHz, which are then written directly into accelerator memory via PCIe peer-to-peer writes. Replies are sent back using a similar mechanism, achieving a total round-trip latency of approximately 0.44 microseconds.

Strategically, the request queue is placed in the accelerator's memory, while the reply queue resides within the FPGA. This design facilitates efficient polling mechanisms on both sides. The interconnect is designed to be modular, allowing for future upgrades or replacements of the physical link without affecting the higher layers of the system.

Heterogeneous Computing for Quantum Error Correction

To meet the demands of real-time QEC, the system supports a heterogeneous computing model. Decoders for FPGAs, CPUs, and GPUs can all operate within the same framework, allowing for flexibility in determining the optimal hardware for specific tasks. The runtime supports multiple programming models, including Python, C, OpenMP, and GPU kernel chains, enabling interoperability and adaptability for various applications beyond error correction, such as calibration, telemetry, and adaptive measurement.

This modular and flexible approach ensures that the system can evolve alongside advancements in quantum and classical computing technologies, paving the way for scalable and fault-tolerant quantum computing systems.